Synchronization of signals

ABSTRACT

A circuit and method are provided to enable the synchronization of an on-demand, synchronous signal with an asynchronous signal. The synchronous signal is activate only for a portion of the period of the asynchronous signal, thus providing beneficial power conservation. The synchronous signal is activated in response to a first edge of the asynchronous signal, and deactivated in response to a second edge of the asynchronous signal.

BACKGROUND OF INVENTION

1. Field of Invention

The invention relates to synchronization of signals, and more specifically to a circuit and method for synchronizing an asynchronous signal with a synchronous, on-demand, oscillating signal.

2. Discussion of Related Art

In processor applications it is often desirable, or even necessary, to synchronize actions performed at a first clock frequency with actions performed at a second clock frequency. For example, read and write operations from registers may be performed at different speeds. For instance, the register may be written to, or updated, once every second, while the circuitry that reads from the register and manipulates, decodes, stores, or otherwise operates on data in the register may be controlled by a clock signal of higher frequency, for example 100 MHz. In such a situation, the circuitry controlled by the 100 MHz clock may complete the manipulation of the data in the register in advance of the register being updated again. If the circuitry controlled by the 100 MHz clock were to continue to read data from the register and manipulate the data, its operation would be redundant, since the register had not yet been updated with new data.

Worse, the continuous operation of the 100 MHz circuitry would be inefficient, since circuits that produce, or are controlled by, oscillating signals often consume power during operation; namely, in the process of changing the state of a signal from low to high, or vice versa. Therefore, circuits which produce, or are controlled by, an oscillating signal with a high frequency are likely to consume more power than a comparable circuit producing, or operating under the control of, an oscillating signal with a low frequency. In effect, substantial power may be consumed in continuously producing a high frequency oscillating signal, despite the fact that the signal is only needed for a portion of the time it is being run. As processor clocking speeds continue to increase, this amount of power will likely increase as well. Thus, efficient circuits and methods for synchronizing an asynchronous signal with an on-demand synchronous signal are needed.

SUMMARY OF INVENTION

One aspect of the invention provides an accurate and power efficient circuit and method for synchronizing an asynchronous signal with an on-demand, synchronous oscillating signal.

According to one aspect of the invention, a method of synchronizing an asynchronous signal having at least a falling edge and a rising edge with a synchronous signal is provided. The method comprises activating the synchronous signal in response to one of the falling edge and the rising edge of the asynchronous signal, and deactivating the synchronous signal in response to the other of the rising edge and the falling edge of the asynchronous signal. According to one embodiment, the synchronous signal exhibits a frequency of oscillation that is great enough to allow the synchronous signal to complete at least one cycle during a time between one of the falling edge and the rising edge and the other of the rising edge and the falling edge.

According to another aspect of the invention, a digital circuit for synchronizing an asynchronous signal having at least a falling edge and a rising edge with a synchronous signal is provided. The synchronous signal exhibits a frequency of oscillation that is great enough to allow the synchronous signal to complete at least one cycle during a time between one of the falling edge and the rising edge and the other of the rising edge and the falling edge. The digital circuit comprises a first AND gate having a first input connected to receive the asynchronous signal, a second input connected to receive a second signal, a third input connected to receive a third signal, and an output to output a first output signal.

BRIEF DESCRIPTION OF DRAWINGS

The accompanying drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. In the drawings:

FIG. 1 illustrates signals of different frequency to which the circuit and method of the present invention may apply. Note that the signals are not drawn to scale.

FIG. 2 is an illustration of a circuit for synchronizing an asynchronous signal with a synchronous, on-demand, oscillating signal according to the present invention.

FIG. 3 is a timing diagram illustrating the synchronization sequence according to the present invention.

DETAILED DESCRIPTION

This invention is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings. The invention is capable of other embodiments and of being practiced or of being carried out in various ways. Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having,” “containing”, “involving”, and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

The present invention will now be described by way of a specific, non-limiting, example. It should be understood that the invention applies to systems and circuits beyond those discussed here. Specific values of frequencies and other circuit parameters are meant for illustrative purposes only, and are non-limiting. For purposes of this application, the term “synchronous” refers to signals and events that occur at specific times of a common timing signal. The term “asynchronous” refers to signals or events which may occur at any time relative to a common timing signal.

An aspect of the invention may apply to any circuit or system with two or more signals, where at least one of the signals is asynchronous and another of the signals is synchronous, and wherein the time duration between consecutive edges of the asynchronous signal is great enough as to allow at least one cycle of the synchronous signal to complete. For example, the present invention may find application in a processor in which multiple clocking domains are provided. FIG. 1 illustrates three signals which may be associated with a processor. It should be noted that the frequencies of the signals in FIG. 1 are not drawn to scale.

A first signal f₁ having a frequency of 32.768 kHz and an equal, 50%, high and low duty cycle may be provided to the processor, or a portion thereof, by a crystal oscillator located externally to the processor. Signal f₁ could also be produced by any other known means for producing an oscillating signal. Signal f₁ could be downsampled to produce an asynchronous signal f₂, having a lower frequency than signal f₁. In this non-limiting example f₂ has a frequency of 1 Hz. It is assumed that signal f₂ includes at least one falling edge and at least one rising edge, as illustrated in FIG. 1. While signal f₁ exhibited a 50% high and low duty cycle, it will be desirable, if possible, to form signal f₂ with the high and low states having unequal duty cycles, for reasons to be discussed later. In this non-limiting example the high state of signal f₂ has a duration of d₂, equal to 999.97 ms, or 32,767 cycles of signal f₁. The low state of signal f₂ has a duration of d₁, equal to 30.52 μs, or 1 cycle of signal f₁. It should be appreciated that in this example d₂ is so much greater than d₁ that d₁ is effectively “zero.” Alternatively, signal f₂ may be produced by other means than those described, which are meant for illustrative purposes only.

Synchronous signal f₃ may be a signal provided by another crystal oscillator, or by any other known methods. The frequency of signal f₃ is such that at least one cycle of f₃ may be completed between any two consecutive edges of f₂. In some cases it may be necessary that f₃ complete at least two cycles between any two consecutive edges of f₂. For example, the frequency of f₃ may be 100 MHz. Alternatively, f₃ could have other frequencies. Signal f₃ is synchronous in that the timing of circuit operations occurs at specific times of f₃, typically at a rising or falling edge of f₃. The falling edge and rising edge of f₂ are both asynchronous, in that they are not required to occur at specific times, but rather, may occur at any time during the cycle of f₃.

One of skill in the art will recognize that the indicated frequency and duty cycle of f₂ are non-limiting, and that the invention applies to any frequency and duty cycle, including signals with equal high and low duty cycles. In fact, all that is necessary is that the asynchronous signal, f₂, has at least a falling edge and at least a rising edge, and that the time duration between any two consecutive edges of f₂ is great enough to allow at least one cycle of signal f₃ to complete. In some cases it may be necessary that f₃ complete at least two cycles between any two consecutive edges of f₂. In other words, f₂ need not be periodic in any way, and the invention may find application in systems where f₂ is not periodic, but rather exhibits random oscillations.

For illustrative purposes only, it will be assumed that signals f₂ and f₃ have specific functions or meanings within the processor. For instance, data may be written to a register on a rising edge of asynchronous signal f₂, i.e., once per second. Signal f₃ may control circuitry that reads data from the register and operates on the data. Signal f₃ is thus an on-demand signal, in that its operation need not be continuous, but rather, is desired after the register has been written to, or updated, i.e., in this non-limiting example, once per second. It is desired to activate synchronous signal f₃ for as short a time as possible so as to save power and minimize redundancy of processor operations. It is thus necessary to determine appropriate times at which to activate and deactivate signal f₃.

While f₃ could be active at any point during the cycle of signal f₂, i.e., during the high state only, the low state only, or a transition between the high and low states, it is simplest to synchronize the operation of f₃ to a transition state (high-to-low, or low-to-high) of asynchronous signal f₂. This is especially true in situations in which f₂ may not be periodic, but rather exhibits random oscillations. Thus, in this non-limiting example it is desired to detect an edge of f₂, so that, for instance, signal f₃ will always be active during the rising edge of f₂, at which time the data written to the register is stable. To accomplish this, the present invention takes advantage of the observation that the asynchronous rising edge of signal f₂ may be foreshadowed by the asynchronous falling edge of f₂. Thus, signal f₃ may be activated in response to the asynchronous falling edge of signal f₂ such that signal f₃ will be active during the ensuing asynchronous rising edge of signal f₂. Signal f₃ may then be deactivated in response to the asynchronous rising edge of signal f₂. By this method, signal f₃ will not be active for the entire period of f₂, so that power will be conserved.

FIG. 2 is an illustration of a circuit according to the present invention. The circuit 200 enables signal f₃ to become active in response to an asynchronous falling edge of signal f₂, and then to become inactive in response to the ensuing asynchronous rising edge of signal f₂. To begin, a signal sclk is input to one input of AND gate 228. In this example, signal sclk is produced externally to the circuit 200, and is used to generate signal f₃. In other words, signal f₃ is a gated version of signal sclk. However, as mentioned previously, signal f₃ could be produced by any other means. Asynchronous signal f₂ is input to synchronization register 210, AND gate 216, and inverter 232. The output of inverter 232 is input to OR gate 230, the output of which, enable, is connected to a second input of AND gate 228. When enable is high the output of AND gate 228, f₃, follows sclk. Signal f₃ is also input to inverter gate 226 to produce signal f₄. Signals f₃ and f₄ are not only provided to circuit 200, but may be provided to other circuitry (not shown), for example circuitry that reads data from a register.

Signals f₃ and f₄ are provided as clocking inputs to synchronization register 210. Synchronization register 210 may be a standard register configured as a synchronization register. When signals f₃ and f₄ are inactive, the output of synchronization register 210, rc_2 f, will be static. When signals f₃ and f₄ are active, the output of synchronization register 210, rc_2 f, follows the input, f₂, with a delay. In particular, when actively clocked, the synchronization register operates to translate any asynchronous edge of f₂ into a synchronous edge of rc_2 f, as will be described further in connection with FIG. 3. Synchronization register 210 may comprise one or more delay latches, and the number of delay latches may be chosen to optimize the settling time of signal rc_2 f, as would be known to one of skill in the art.

Signal rc_2 f is input to one terminal of AND gate 216, to delay register 212, and to one input of NAND gate 222. Delay register 212 can be a standard digital delay register, and may function as a combination of two delay latches. Delay register 212 is clocked by signals f₃ and f₄, so that when signals f₃ and f₄ are active the output rc_4 f will be a delayed version of the input, rc_2 f. In this non-limiting example, the delay is equivalent to one cycle of signal f₃. However, any number of delay registers could be used to achieve a desired delay, and the invention is not limited to any specific number of delay registers. Signal rc_4 f is input to inverter 214, the output of which is input to AND gate 216. Thus, AND gate 216 receives f₂, rc_2 f, and an inversion of rc_4 f as inputs. The output of AND gate 216, OUT, is input to inverter 218, the output of which is input to NAND gate 220. The output of NAND gate 220 is a second input to NAND gate 222. A second input of NAND gate 220 is the output of delay register 224, run_clk_2 f. Delay register 224 is clocked by signals f₃ and f₄, and receives the output of NAND gate 222 as an input. Delay register 224 may be a standard digital delay register, and may function as a combination of two delay latches. In this non-limiting example, run_clk_2 f is delayed a duration of one cycle of signal f₃ from the output of NAND gate 222 by delay register 224. However, any number of delay registers could be used to obtain a desired delay duration, and the invention is not limited to any specific number of delay registers. It should also be appreciated that the combination of NAND gate 220, NAND gate 222, and delay register 224 operates as a synchronous set/reset circuit of signal run_clk_2 f, and could be replaced by any standard synchronous set/reset circuit. It should also be appreciated that the circuit of FIG. 2 prevents unwanted transitions of the signal OUT, which may otherwise arise due to uncertain states of digital components or unclean rising and falling edges of circuit signals.

The operation of circuit 200 will now be described with reference to FIG. 3. Prior to a time t₀ it is assumed that f₂ is in a high state, and that the circuit 200 has had time to stabilize. In general, signal rc_2 f is static when signals f₃ and f₄ are not active, and follows signal f₂ when signals f₃ and f₄ are active. It is assumed that prior to t₀ signal rc_2 f is high and in a static state, and therefore the inversion of signal rc_4 f is low, so that OUT is also low. The output of inverter 218 is thus high. The delay register 224 must initially be set low, but subsequently the circuit operation will return the output to its initially low state without the need for external intervention. Thus, it is assumed that prior to t₀ the output of delay register 224, run_clk_2 f, is low. Since the output of delay register 224 is low, as is the output of inverter 232, enable is also low, so that signals f₃ and f₄ are inactive. The signal sclk is active.

As illustrated, an asynchronous falling edge of f₂ occurs at some time between times t₀ and t₁. As mentioned, since f₂ is asynchronous it may have a falling edge or rising edge at any time relative to the cycle of f₃, and thus is not restricted to transition at any fixed time of the cycle of f₃, such as t₀, t₁, t₂, t₃, etc. The output of inverter 232 is driven high, so that enable also has an asynchronous rising edge. Therefore, signals f₃ and f₄ are asynchronously triggered, in response to the asynchronous falling edge of signal f₂. With signals f₃ and f₄ active, synchronization register 210 is actively clocked, so that signal rc_2 f follows signal f₂ with a synchronous falling edge. However, since it takes some time for the signals f₃ and f₄ to propagate to synchronization register 210, it is not known at exactly what time signal rc_2 f has a falling edge. It is known that the falling edge of rc_2 f will occur at some time t₁ or t₃, as indicated by the cross-hatching. Accordingly, signal rc_4 f will also display a falling edge at time t₃ or t₅, respectively, appropriately delayed from the falling edge of signal rc_2 f by one cycle of signal f₃. As mentioned, any number of delay registers 212 could be used to obtain a desired delay duration of signal rc_4 f, and the invention is not limited to any specific number of delay registers. With OUT and rc_2 f low, the output of NAND gate 222 will be driven high. Thus, the output of delay register 224, run_clk_2 f, displays a corresponding rising edge at time t₃ or t₅. Thus, if the asynchronous falling edge of f₂ occurs at any time between t₀ and t₁, the circuit 200 reaches a stable state by time t₅. No further changes will occur during the time t₅-t₁₂.

The importance of AND gate 216 should be realized. Since the falling edge of f₂ is asynchronous, it may occur at any time, for example, in the range from t₀ to t₂. If the asynchronous falling edge occurs at a point in the cycle of sclk for which sclk is in a low logic state, for instance between times t₁ and t₂, no problems arise. However, if the asynchronous falling edge occurs at a time at which sclk is in a high logic state, problems may arise. More specifically, as shown, the falling edge of f₂ occurs between times t₀ and t₁. Thus, signal f₃ assumes a high logic state for a shortened period of time, i.e., from the time of the asynchronous falling edge of f₂ to time t₁, which is shorter in duration than the normal high logic state would be; specifically, from time t₀ to t₁. This shortened feature of signal f₃ may be referred to as a glitch, and the design of circuit 200 accounts for such undesired glitches. If this shortened high logic state of signal f₃ is allowed to control circuitry, such as registers, read and write operations may not be completed appropriately, since the read and write operations may require a longer processing time than the time from the asynchronous falling edge of f₂ until time t₁. An undesired output OUT may occur. However, by providing a third input, signal f₂, to AND gate 216, the asynchronous falling edge of f₂ acts to prevent any unwanted circuit behavior that f₂ itself may cause due to its asynchronous nature.

At some time between t₁₂ and t₁₄, an asynchronous rising edge of signal f₂ occurs, as indicated by the slash marks. Since signals f₃ and f₄ are active, signal rc_2 f will synchronously follow the rise of f₂, with an appropriate delay, at time t₁₅. Since f₂ and rc_2 f are high, and the inversion of signal rc_4 f remains high, due to the fact that the rising edge has not yet propagated through delay register 212, the output OUT displays a rising edge at time t₁₅. Signal rc_4 f will display a rising edge at a time t₁₇, and the inversion of rc_4 f will display a falling edge at the same time, thus driving signal OUT low. Thus, the signal OUT displays a single pulse between t₁₅ and t₁₇ that indicates a rising edge of f₂ has occurred. Such a pulse could be used, for instance, to activate a read operation from a register.

With rc_2 f high, and the output of NAND gate 220 also high at time t₁₅, the output of delay register 224, run_clk_2 f, will be driven low at time t₁₇. With run_clk_2 f low, and the output of inverter 232 also low, enable will be driven low at time t₁₇, thus deactivating signals f₃ and f₄. In this manner, then, signal f₃ was only active for a portion of the operation time of the circuit. As discussed previously in connection with FIG. 1, if the duration of the low state of f₂ is 30.52 μs, while the duration of the high state of f₂ is 999.97 ms, then signals f₃ and f₄ are almost always deactivated. Thus, considerable power savings may be realized. However, it should be appreciated that the circuit of FIG. 2 will operate appropriately regardless of the duty cycles of the high and low states of signal f₂. It should also be appreciated that the asynchronous rising edge of f₂ may occur at any point between times t₁₂ and t₁₄, with the remaining signals of FIG. 3 remaining unchanged. It should also be realized that signal f₂ has been described as an active low signal, but an active high signal could also be used by inputting the active high signal into an inverter, and then into circuit 200 at the point of f₂.

The importance of OR gate 230 should also be realized. As described, combining asynchronous and synchronous signals in a circuit may lead to undesired or unexpected behavior, such as glitches. While the asynchronous falling edge of f₂ may trigger enable asynchronously, thus leading to asynchronous edges of f₃ and f₄, the asynchronous rising edge of f₂ will always precede a synchronous falling edge of enable. This is because signal run_clk_2 f is a synchronous signal, and the synchronous falling edge of run_clk_2 f drives the signal enable low. Thus, signals f₃ and f₄ are deactivated with synchronous edges, so that they do not exhibit any glitches upon deactivation. This characteristic may improve the stability of circuit 200 or other circuitry controlled by signals f₃ or f₄.

As mentioned, any number of delay registers can be used in place of delay registers 212 and 224 to optimize the operation of circuit 200 for specific considerations. The addition of delay at the point of delay register 212 would function to increase the duration of the high state pulse of signal OUT. The addition of delay at the point of delay register 224 would function to shift the pulse of run_clk_2 f to a later point in time, depending on the amount of delay added. Additionally, delay registers may be added between signal OUT and inverter 218. Such delay registers may function to prolong the active state of signal f₃ and f₄ beyond the asynchronous rising edge of signal f₂. For example, the addition of a single delay register between OUT and inverter 218 may maintain f₃ and f₄ in an active state for a duration of one cycle of f₃ beyond the asynchronous rising edge of signal f₂. Each additional delay register may function to prolong the active state of f₃ and f₄ by an additional cycle of signal f₃. The addition of such delay registers would also function to maintain the high logic states of signals enable and run_clk_2 f for as long as signals f₃ and f₄ remain active. Signals f₂, rc_2 f, rc_4 f, OUT, and sclk would be unaffected by the addition of delay registers between OUT and inverter 218.

As mentioned in the description of FIG. 2, the combination of NAND gate 220, NAND gate 222, and delay register 224 operates as a synchronous set/reset circuit of signal run_clk_2 f. More specifically, signal run_clk_2 f is set high by a low state of rc_2 f, and then signal run_clk_2 f is reset to a low state by a high state of OUT. Thus, the combination of NAND gate 220, NAND gate 222, and delay register 224 could be replaced by any standard synchronous set/reset circuit that receives signals rc_2 f and OUT as inputs, and outputs signal run_clk_2 f.

Also, it should be noted that in this non-limiting example signals f₃ and f₄ have been described as gated versions of signal sclk. However, signals f₃ and f₄ could alternatively be formed as non-overlapping clock signals, without departing from the nature of the invention. Signal sclk could be input to a non-overlapping clock generator, as would be known to one skilled in the art. Signals f₃ and f₄ could then be out-of-phase with each other, with each signal exhibiting a longer low state duty cycle than high state duty cycle. For example, the low states of f₃ and f₄ could have a 54% duty cycle, while the high states could have a 46% duty cycle. The invention is not limited to any specific high and low duty cycles of signals f₃ and f₄.

Having thus described several aspects of at least one embodiment of this invention, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description and drawings are by way of example only. 

1. A method of synchronizing an asynchronous signal having at least a falling edge and a rising edge with a synchronous signal, the method comprising acts of: activating the synchronous signal in response to one of the falling edge and the rising edge of the asynchronous signal; and deactivating the synchronous signal in response to the other of the rising edge and the falling edge of the asynchronous signal; wherein the synchronous signal exhibits a frequency of oscillation that is great enough to allow the synchronous signal to complete at least one cycle during a time between one of the falling edge and the rising edge and the other of the rising edge and the falling edge.
 2. The method of claim 1, wherein the at least one cycle includes at least two cycles.
 3. The method of claim 1, wherein the asynchronous signal has unequal low and high duty cycles.
 4. The method of claim 1, wherein the asynchronous signal exhibits random oscillations of the rising edge and the falling edge.
 5. The method of claim 1, wherein the asynchronous signal exhibits repeating oscillations at fixed intervals of the rising edge and the falling edge.
 6. The method of claim 1, wherein the synchronous signal is activated at substantially the same time as the one of the falling edge and the rising edge of the asynchronous signal.
 7. The method of claim 1, wherein the synchronous signal remains active for a duration of two cycles of the synchronous signal after the occurrence of the other of the rising edge and the falling edge of the asynchronous signal.
 8. The method of claim 1, wherein the act of activating the synchronous signal in response to one of the falling edge and the rising edge of the asynchronous signal includes providing a first logic gate having an input connected to receive an inversion of the asynchronous signal and an output to output a signal to activate the synchronous signal.
 9. A digital circuit for synchronizing an asynchronous signal having at least a falling edge and a rising edge with a synchronous signal, wherein the synchronous signal exhibits a frequency of oscillation that is great enough to allow the synchronous signal to complete at least one cycle during a time between one of the falling edge and the rising edge and the other of the rising edge and the falling edge, the digital circuit comprising: a first AND gate having a first input connected to receive the asynchronous signal, a second input connected to receive a second signal, a third input connected to receive a third signal, and an output to output a first output signal.
 10. The digital circuit of claim 9, further comprising a first delay register having an input connected to receive the second signal and an output to output an inversion of the third signal.
 11. The digital circuit of claim 9, further comprising: a synchronization register having an input connected to receive the asynchronous signal and an output to output the second signal.
 12. The digital circuit of claim 11, wherein the synchronization register has a first clock input connected to receive the synchronous signal.
 13. The digital circuit of claim 9, further comprising a synchronous set/reset circuit having a first input connected to receive an inversion of the first output signal, a second input connected to receive the second signal, and an output to output a fourth signal.
 14. The digital circuit of claim 13, wherein the synchronous set/reset circuit comprises a first NAND gate having a first input connected to receive an inversion of the first output signal, and a second input connected to receive the fourth signal.
 15. The digital circuit of claim 14, wherein the synchronous set/reset circuit further comprises a second NAND gate having a first input connected to receive an output of the first NAND gate, and a second input connected to receive the second signal.
 16. The digital circuit of claim 15, wherein the synchronous set/reset circuit further comprises a second delay register having an input connected to receive an output of the second NAND gate, and an output to output the fourth signal.
 17. The digital circuit of claim 16, wherein the second delay register has a first clock input connected to receive the synchronous signal.
 18. The digital circuit of claim 13, further comprising: a first OR gate having a first input connected to receive an inversion of the asynchronous signal, and a second input connected to receive the fourth signal.
 19. The digital circuit of claim 18, further comprising a second AND gate having a first input connected to receive an output of the first OR gate, and a second input connected to receive a clock signal. 20 The digital circuit of claim 19, wherein the output of the second AND gate is the synchronous signal.
 21. The digital circuit of claim 9, wherein the wherein the synchronous signal exhibits a frequency of oscillation that is great enough to allow the synchronous signal to complete at least two cycles during a time between one of the falling edge and the rising edge and the other of the rising edge and the falling edge. 